Circuits used for signal conditioning in extreme environments, such as High-Temperature High Pressure (HTHP) wells in the down-hole oil exploration industry, often have stringent operating requirements. These requirements arise from the fact that these extreme environments affect the performance characteristics of such circuits. For example, in the down-hole oil exploration industry, temperatures may range from −55° C. to 225° C. High temperatures in particular can have serious detrimental effects on circuit performance.
Generally, in signal conditioning systems such as HTHP, an amplifier is used to buffer high-impedance sensor (DC-coupled) outputs. In extreme environments, performance characteristics such as input offset current, offset voltage, and low-frequency noise response are important considerations for such an amplifier. The materials and processing methods used to fabricate an amplifier directly determine performance characteristics. For example, Silicon-On-Insulator (SOI) CMOS substrates and SOI CMOS processing techniques have been shown to yield amplifiers with reduced leakage currents and other enhanced characteristics (e.g., reduced device latch-up).
Despite the advantages of using SOI CMOS, issues related to input offset voltage (and current) and low 1/f noise for DC/low-frequency amplifier applications have not been fully addressed. Consequently, ping-pong auto-zeroed amplifiers have been developed to address these issues. These amplifiers produce a low input offset voltage and low 1/f noise by an auto-zeroing process. The auto-zeroing process periodically alternates, or “ping-pongs,” between a ping amplifier and a pong amplifier. When a ping amplifier is providing amplification, the pong amplifier corrects itself for input offset voltage, or “auto-zeroes.” After a predetermined time, the pong amplifier provides amplification and the ping amplifier auto-zeroes.
A Basic Ping-Pong Amplifier (BPPA) 10 is illustrated in FIG. 1A. BPPA 10 includes two matched amplifiers 12 and 14. Amplifiers 12 (PING AMP) and 14 (PONG AMP) may be viewed as the primary amplifiers of BPPA 10. PING AMP 12 and PONG AMP 14 each respectively include a pair of primary differential inputs 16 and 18, an auxiliary pair of differential inputs 20 and 22, and single-ended outputs 24 and 26. The primary inputs 16 and 18 are each switchably coupled to −Input 28 and +Input 30 (which receive an externally applied differential input signal). The auxiliary differential inputs 20 and 22 receive offset voltage correction signals. Single-ended outputs 24 and 26 are coupled to output stage 44 to produce a BPPA 10 output signal at node 46.
Also included in BPPA 10 are switches 51-60. Switches 51-60 form a switching network which is used to couple −Input 28 and +Input 30 to PING AMP 12 and PONG AMP 14, VREF 40 to one side of differential auxiliary inputs 20 and 22, and outputs 24 and 26 to output stage 44. Switches 51-60 are controlled by a two-phase non-overlapping clock (not shown). Switches 51-55 are switched by one phase of the clock and switches 56-60 are switched by the other phase of the clock. A transmission gate may be used to implement switches 51-60. An example timing diagram of a two-phase non-overlapping clock signal used to open and close switches 51-60 is illustrated in FIG. 1B.
As described above, PING AMP 12 and PONG AMP 14 alternately drive output stage 44 (by amplifying the externally applied differential signal) or are being auto-zeroed. If PING AMP 12 is being auto-zeroed, for example, switches 56-58 are closed and switch 52 is open, thereby preventing PING AMP 12 and PONG AMP 14 from shorting together. During this time, output 24 is nulled to a voltage VA. VA may be roughly calculated to be:VA≈(gmA1/gmA2)*VosA+VREF40where gmA1 and gmA2 are the respective transconductances of the primary differential pair (coupled to inputs 16) and the auxiliary differential pair (coupled to inputs 20) within PING AMP 12. VosA is an input offset voltage intrinsic to PING AMP 12. A correction voltage to compensate for VosA is forced onto capacitors 32, 34, and auxiliary differential input 20 when switches 57 and 58 are closed (PING AMP 12 auto-zeroing). When 57 and 58 are opened at the end of the PING AMP 12 auto-zero phase, capacitors 32 and 34 store the correction voltage and communicate it to input 20 during the PING AMP 12 amplification phase. VosA is thus nulled out.
Similarly, when PONG AMP 14 is auto-zeroed, output 26 is nulled to a voltage VB. VB may be roughly calculated to be:VB≈(gmB1/gmB2)*VosB+VREF40where gmB1 and gmB2 are the respective transconductances of the primary differential pair coupled to inputs 18 and the auxiliary differential pair coupled to auxiliary inputs 22. Analogous to PING AMP 12, an offset correction voltage is also stored (during auto-zeroing) and communicated (during amplification) via capacitors 36 and 38.
By periodically ping-ponging between PING AMP 12 and PONG AMP 14, capacitors 32-38 are refreshed and the overall amplifier remains auto-zeroed. In HTHP applications this may be done at a predetermined frequency so that if capacitors 32-38 and other circuit components within BPPA 10 dissipate in charge or drift in value, frequent refreshing assures an accurate offset voltage correction of PING AMP 12 and PONG AMP 14 will be maintained.
While basic ping-pong amplifiers provide a substantial reduction in input offset voltage, the output signal at node 46 may be impacted by transient glitches attributable to ping-ponging between PING AMP 12 and PONG AMP 14. For example, the voltage level used to drive output stage 44 (at node 48) may be generally around the voltage level of VREF 40. However, when PONG 12 is initially switched (via switch 52) to drive output stage 44, a transient voltage difference (or glitch) of about (gmA1/gmA2)*VosA will be communicated to node 48. Likewise, when PONG AMP 14 is initially switched (via switch 60) to node 48, a transient voltage difference of about (gmB1/gmB2)*VosB will be communicated to node 48. As the system adjusts and corrects for these error terms, exaggerated transient glitches at node 46 are produced.
The residual voltage difference from what is required at node 48 is ultimately corrected by feedback from external resistors that set the overall ping-pong amplifier closed-loop gain. Feedback will adjust the differential voltages at differential inputs 16 or 18 to what is needed to correctly position node 48. This correction in effect produces a small input offset error in PING 12 and PONG 14, owing to their finite voltage gain. The offset error generally differs between PING 12 and PONG 14, which introduces the undesirable effect of an offset voltage “square wave” as the system ping-pongs between PING 12 and PONG 14. This “square wave” will be amplified by the closed-loop gain of the overall ping-pong amplifier and appears at output node 46. The edges of the square wave will generally have exaggerated transient overshoot glitches, similar to the effect shown in FIG. 1C. Additionally, the transient glitch magnitude may be further exacerbated by charge injection effects from switches 51-60.
These transient glitches and “square wave” effect may be problematic to downstream circuits that receive them. Therefore, there is a need for a ping-pong amplifier with improved auto-zeroing.